By 2025, the race for AI chip performance is heating up like never before. With the launch of NVIDIA's Blackwell and AMD's MI400 series, demand for high bandwidth memory (HBM) has surged nearly 300 percent. Traditional packaging technologies are struggling to keep up. That's where CoPoS, short for Chip on Panel on Substrate, comes in. This next-gen packaging technology is quickly emerging as a promising solution in the field of advanced semiconductor packaging.

Catalog

I. What Is CoPoS Packaging?

II. Key Advantages of CoPoS

III. CoPoS vs CoWoS

IV. Tackling RDL and Glass Substrate Challenges

V. Conclusion

I. What Is CoPoS Packaging?

CoPoS is an innovative packaging approach built on panel-level packaging (PLP), enhanced by the addition of an interposer layer. Unlike conventional fan-out wafer-level packaging (FOWLP), CoPoS integrates the interposer on a large panel substrate, enabling better signal integrity and more stable power delivery. This structure is especially well-suited for high-end devices that combine GPUs and high bandwidth memory.

II. Key Advantages of CoPoS

· High-density interconnects: The interposer enables much higher I/O density, meeting the demanding needs of AI and high-performance computing (HPC) applications.

· Excellent signal integrity: The interposer helps reduce electrical interference, ensuring stable and reliable signal transmission.

· Strong thermal performance: The architecture supports better heat dissipation, helping reduce chip temperatures and improve overall system reliability.

· Panel size scalability: CoPoS uses large panels (such as 510mm x 515mm), increasing chip placement density and reducing cost per unit.

III. CoPoS vs CoWoS

CoWoS, known as a leading 2.5D multi-die packaging solution, has already gained wide adoption in high-performance systems. NVIDIA's CoWoS-based products now account for over half of the computing power on the TOP500 supercomputer list.

The key innovation with CoPoS is that it uses panel-level RDL (redistribution layer) processes and square substrates to achieve higher integration efficiency. This not only boosts production yields and capacity but also lowers overall manufacturing costs. Whether using traditional organic substrates or new glass substrates, CoPoS can adapt to both, offering another path for dense I/O layouts. Its architecture is also compatible with advanced assembly flows like chip-last, making it an ideal choice for integrating heterogeneous chips in AI systems.

Compared to CoWoS, CoPoS improves production throughput and cost efficiency through its panel-based approach.

IV. Tackling RDL and Glass Substrate Challenges

The RDL layer is at the heart of the CoPoS interconnect system. It redistributes chip signals and enables high-density multi-layer wiring between the chip and substrate.

As CoPoS evolves, RDL processes are being pushed to higher levels of precision. Under the RDL-first trend, the process demands highly uniform film thickness and ultra-fine patterning, requiring tight control of plating current density. Manz, a key equipment provider, addresses this with vertical electroplating tools using multi-anode systems and jig-free designs that can manage nanoscale copper grain structure. Their modular wet processing equipment also ensures micro-level surface roughness control (<0.5μm), which is essential for free-form RDL routing.

Meanwhile, glass substrates are becoming a key enabler for next-generation packaging, thanks to their superior electrical properties and dimensional stability. Compared to organic substrates like ABF and traditional silicon interposers, glass offers advantages in thermal expansion control, surface quality, and process compatibility—but only when paired with precision equipment.
Manz's automated solutions support ultra-thin glass handling across large panel sizes (300mm to 600mm) and offer uniform development and etching. They also offer dual-mode tooling compatible with both dry film and organic dielectric layers to support mixed-material processes in 2.5D and 3D packaging.

In terms of process integration, equipment parameters must be tightly coupled with material characteristics. For example, ABF buildup layers require uniform 3μm copper thickness at high current densities (10ASD), while glass-based TGV vias need deep etching capabilities with 10:1 aspect ratios. Manz's proprietary technologies provide a scalable equipment platform to support the continued evolution of CoPoS.

V. Conclusion

As companies like Google DeepMind push chip design forward with AI-driven tools such as Gemini Deep Think, packaging innovation is evolving in lockstep with algorithm breakthroughs. CoPoS doesn't just solve CoWoS's bottlenecks in production—it's redefining the future of chip packaging altogether.

CoPoS signals a shift toward a "packaging as system" paradigm, blurring the line between chips and system boards. It transforms thermal management from a passive afterthought into an integrated design factor, and reimagines the PCB not just as a connector but as a functional platform.

In short, CoPoS isn't just a new technology—it's a new mindset for building the next generation of intelligent computing hardware.