What is CoWoP Packaging?
Recently, there's been a lot of buzz in the industry that NVIDIA is considering adopting a new packaging technology called CoWoP (Chip-on-Wafer-on-Platform PCB) for its next-generation Rubin GPUs. This new solution reportedly offers several advantages and could become NVIDIA's next go-to packaging method. But what exactly is CoWoP? In this article, we'll dive into what CoWoP is, its benefits, and how it stacks up against the existing CoWoS technology.
Catalog
II. Key Features and Advantages
I. What is CoWoP Packaging?
CoWoP stands for "Chip-on-Wafer-on-PCB." Simply put, it's a packaging method where the chip is flip-chip bonded through a silicon interposer directly onto a high-density PCB (Printed Circuit Board), eliminating the need for the traditional organic substrates like ABF or BT boards and the usual BGA solder balls. This creates a more integrated connection between the chip and the PCB. CoWoP combines the high-performance interconnect advantages of silicon interposers with the cost benefits of PCBs, making it the next evolution beyond CoWoS (Chip-on-Wafer-on-Substrate) system-level packaging.
II. Key Features and Advantages
Industry reports highlight seven major benefits that CoWoP brings to the table:
1. Improved Signal Integrity (SI): By cutting out a layer of packaging substrate and using micro-bump flip-chip connections through the silicon interposer directly to the PCB, signal paths become shorter and more direct. This significantly reduces communication losses for high-speed links like NVLink and HBM and can extend transmission distances.
2. Enhanced Power Integrity (PI): Traditional CoWoS packages have voltage regulators (VRs) located on the PCB or packaging substrate, creating long power delivery paths to the GPU die. This introduces parasitic resistance, capacitance, and inductance—collectively called parasitic parameters—that cause power loss, voltage fluctuations, and delayed responses. CoWoP allows VRs to be integrated much closer to the GPU die, drastically shortening power paths, reducing parasitic effects, stabilizing voltage, minimizing noise, and improving power efficiency especially under heavy loads.
3. Better Thermal Performance: Reduced power loss means less heat generation. Coupled with CoWoP's lidless design, which allows the heat sink to directly contact the GPU die, this leads to more efficient heat dissipation.
4. Reduced PCB Thermal Expansion and Warping: The lower coefficient of thermal expansion (CTE) in PCBs used for CoWoP helps address warping issues, improving overall mechanical stability.
5. Improved Electromigration: Optimized current paths and reduced parasitic resistance decrease the risk of electromigration, extending chip longevity.
6. Lower ASIC Cost and Design Complexity: CoWoP eliminates the need for expensive ABF/BT organic substrates and BGA solder balls, cutting material costs (no package or lid) and simplifying manufacturing processes.
7. Supports More Flexible Chip Module Integration: CoWoP paves the way toward a long-term vision of package-less architectures by enabling more modular and adaptable chip integration.
According to industry estimates, CoWoP replaces costly ABF substrates (which can account for over 40% of packaging costs) with large-format PCB panels. Along with the elimination of BGA solder balls and lids, this can cut costs by 30% to 50%. Leveraging mature PCB production lines also shortens delivery cycles significantly—PCB line expansions take about 6 to 12 months, much faster than the two-year expansion cycles typical for traditional substrate lines. This agility is crucial to meet the explosive demand for AI computing hardware.
III. CoWoP vs. CoWoS
Feature | CoWoS Packaging | CoWoP Packaging | Core Difference |
Structure Layers | Chip–Interposer–ABF substrate–PCB | Chip–Interposer–PCB | Eliminates substrate layer |
Wiring Density | Sub-10 μm line width/spacing | 20-35 μm line width/spacing (mSAP process) | 2-3x difference in precision |
Thermal Management | Heat spreader + substrate cooling | Heat sink directly contacts chip + low CTE PCB | 25% lower thermal resistance |
Production Flexibility | Dependent on TSMC capacity, ~24 months | PCB line upgrades, 6–12 months | Greater capacity flexibility |
Cost Structure | ABF substrate >40% of total cost | Removes substrate + BGA steps | 30–50% cost reduction |
Industry insiders believe if CoWoP technology progresses smoothly, the motherboard effectively becomes the chip's "final packaging layer," not only cutting overall costs but also redefining the AI hardware platform landscape. However, some PCB manufacturers argue that current substrate technologies are mature and cost-effective, so CoWoP will still take time to replace traditional packaging.
IV. Conclusion
Forecasts suggest that if global CoWoS demand reaches 700,000 wafers in 2025, even a 20% market share shift to CoWoP could generate a new $7 billion ecosystem. Combined with penetration into consumer electronics and other sectors, the overall market potential could surpass $10 billion. CoWoP packaging isn't just a technology upgrade; it represents a fundamental restructuring of semiconductor industry value chains.
Looking ahead, NVIDIA is expected to collaborate with TSMC, Siliconware Precision Industries (SPIL, a subsidiary of ASE Group), as well as PCB and equipment suppliers, to explore the feasibility of CoWoP packaging on 450mm × 450mm panels at the upcoming supply chain forum in September 2025.
